AMD has published a set of spots for the company’s EDAC (Mistake Discovery and Correction) chauffeur code for the next-generation EPYC CPUs based upon the Zen 4 microarchitecture. The new patches indicate that the approaching CPUs will support each outlet’s unmatched memory bandwidth and capacity.
The spots (found by Phoronix) generate support for DDR5 registered DIMMs (RDIMMs) and DDR5 load-reduced DIMMs (LRDIMMs) for the fourth-generation EPYC CPUs codenamed Genoa (Family 19h Models 10h-1Fh and A0h-AFC CPUs).
The spots also confirm that the upcoming EPYC 7004-series will support up to 12 memory controllers for each outlet, up from 8 for AMD’s current web server components. Sadly, we do unknown how many DIMMs each network (DPC) the chips will support.
Twelve 64-bit DDR5 memory networks
In theory, twelve 64-bit DDR5 memory networks would undoubtedly increase the memory bandwidth available to Genoa CPUs to a massive 460.8 GB/s each outlet, a considerable increase compared with the 204.8 GB/s available current-generation EPYC CPUs with DDR4-3200.
Memory bandwidth alone will not just improve next-generation EPYC ‘Genoa’ CPUs. Twelve memory networks will also enable higher memory capabilities for the new processors. Samsung has already shown 512GB DDR5 RDIMMs and confirmed that 768GB DDR5 RDIMMs were feasible. Also, using 12 512GB components, AMD’s next-generation web server CPUs could support up to 6TB of memory (up from 4TB today).
However, if Genoa supports 2 RDIMMs in each network, that capacity will stretch up to 12TB of DDR5. AMD could increase the capacity per memory network and per outlet further With LRDIMMs (because of octal-ranked component architecture), albeit at the cost of efficiency.
AMD’s EPYC 7004-series ‘Genoa’ CPUs will bring concrete memory improvements compared with current web server CPUs, which will naturally improve their real-world efficiency.
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